A non-volatile memory device typically comprises multiple memory cells interconnected via Word Lines (WLs) and Bit lines (BLs) forming a memory array. Methods for handling defective BLs are known in the art. For example, U.S. Pat. No. 7,447,066 describes a scheme in a memory array having redundant columns, which allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be used for the scheme, or firmware in the memory controller can implement the scheme.
U.S. Pat. No. 6,813,184 describes a NAND flash memory that includes a data loading circuit providing a program data bit into a page buffer having first and second latches. During a data loading operation for programming, the data loading circuit puts a pass data bit into a page buffer corresponding to a defective column, instead of a program data bit that is assigned to the defective column, responding to information of a column address involved in the defective column. It is available to provide a pass/fail check circuit for program-verifying without employing a fuse arrangement, making data of the defective column not affect a program-verifying result.